1. Field of the Invention
The invention relates generally to semiconductor packaging, and specifically to semiconductor packages having stacked semiconductor chips.
2. Description of Related Art
A typical semiconductor package includes a semiconductor chip mounted to a substrate. The substrate may be a metal leadframe with radiating metal leads, or an insulative sheet with metal traces on the sheet and conductive balls serving as the input/output terminals of the package. The chip includes an active surface with rows of bond pads along the peripheral edges of the active surface, and an inactive surface opposite the active surface. The bond pads of the active surface are each electrically connected to the substrate by electrical conductors, such as wire bonds or TAB bonds. The bond pads also may be electrically connected to the substrate in a flip chip style electrical connection, in which case the bond pads face the leads or traces of the substrate and are electrically connected thereto. A hardened insulative encapsulant material covers the chip and a portion of the substrate.
As computers and other types of electronic products become physically more compact and operate at faster speed, miniaturization of components and greater packaging density has become desirable. One approach to meeting this need has been to stack a plurality of chips in one package. Each of the chips is electrically connected to the substrate, and often the chips are electrically connected to each other, especially in memory applications. Where the bottom chip of a stack has a larger horizontal surface area than the top chip of the stack, it is easy to electrically connect the chips to the substrate, since the bond pads of both the upper and lower chips are accessible to a wire bonding machine. However, where the two chips are the same size in that they have the same horizontal surface area, e.g., the chips are identical memory chips, stacking is problematic because of interference between the bond wires connected to the lower chip and the upper chip. One approach to resolving such problems has been to attach a relatively thick spacer (e.g., an adhesive layer or film, or a silicon pad) between the active surface of the lower clip and the inactive surface of the upper chips to provide clearance for wire bonds to the lower chip. However, such a spacer increases package height, among other possible drawbacks. Accordingly, there is a need for a new approach to stacking two or more same size chips in a thin semiconductor package.
The present invention includes semiconductor packages that have at least a pair of semiconductor chips stacked one on top of the other. The stacked semiconductor chips are electrically connected to an interconnective substrate, such as a BGA or LGA style substrate or a metal leadframe. Methods of making such packages are also within the present invention.
In one embodiment, first and second semiconductor chips of the same size and type are provided, with each having an active surface with peripheral bond pads and an opposite inactive surface. The inactive surface of the first semiconductor chip is attached to the substrate. Bond pads of the first semiconductor chip are electrically connected to the substrate using bond wires. A standoff stitch bonding technique may be used to connect the bond wires to the bond pads, resulting in a metal bump on the respective bond pad and a low angle bond wire. The second semiconductor chip is provided with metal bumps on its bond pads. The second semiconductor chip is superimposed over the first semiconductor chip so that the metal bumps and underlying bond pads of the second semiconductor chip are each juxtaposed with a corresponding metal bump and underlying bond pad of the first semiconductor chip. The juxtaposed pairs of metal bumps are fused, resulting in an electrical interconnection of the corresponding bond pads of first and second semiconductor chips and an electrical connection through the respective bond wire to the substrate. An alternative embodiment replaces the metal bumps of the second semiconductor chip with a layer of an anisotropic conductive film.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.